fix: medium ARM bugs + cross-compilation pipeline design#60
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Medium bug fixes (7 issues from embedded code review): - M2: B.W branch offset J1/J2 encoding follows ARM T4 spec - M3: Binary reset handler uses MOVW/MOVT, .data copy + .bss zero loops - M4: ELF entry point has Thumb bit set for ARM targets - M5: STT_FUNC symbol values have Thumb bit set - M6: R10 (memory size) initialized in startup code via MOVW/MOVT - M8: Vector table alignment increased to 256 bytes (was 128) - M10: MPU device() preset sets bufferable=true (was identical to strongly_ordered) Cross-compilation pipeline design: - docs/design/cross-compilation-pipeline.md — 3-phase plan: Phase 1: bare-metal (synth → module.o → ld → firmware.elf → Renode) Phase 2: Zephyr (assembly path via west build + gale module) Phase 3: hardware (STM32F4-Discovery, nRF52840-DK) - artifacts/cross-compilation.yaml — 12 artifacts (XC-001..009, XC-TR-001..003) - artifacts/gale-integration.yaml — 9 artifacts (GI-001..005, GI-TR-001..002, GI-VER-001..002) - rivet.yaml — added gale as external reference Implements: FR-005 Fixes: NFR-002 Trace: skip Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
252 artifacts across 17 types. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Medium Bug Fixes (7 issues)
Cross-Compilation Pipeline Design
docs/design/cross-compilation-pipeline.md— 3-phase plan from bare-metal through Zephyr to real hardwareTest plan
cargo test --workspace— 851 tests, 0 failurescargo clippy— cleancargo fmt --check— clean🤖 Generated with Claude Code