feat: critical ARM fixes, WASM SIMD/Helium MVE, code-gen STPA#59
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Critical/high bug fixes:
- C1: Division by zero now trapped (CMP+BNE+UDF guard before SDIV/UDIV)
- C2/C3: Constant materialization uses MOVW/MOVT for full 32-bit range
- C4/C5: Register allocator excludes R9/R10/R11 from temp allocation
- H2: Bounds check accounts for access size
- H3: Callee-saved registers preserved (PUSH/POP R4-R11,LR)
- H4: 8-byte stack alignment enforced
- H5: Inline i64 division no longer does POP {PC}
- H7: Popcnt uses scratch register instead of R11
- H8: I64SetCondZ uses 32-bit CMP for high registers
WASM SIMD → Helium MVE (Cortex-M55):
- 90 v128 WasmOp variants (i8x16, i16x8, i32x4, i64x2, f32x4)
- 40 MVE ArmOp variants with ISA gating (has_helium())
- Q-register allocator (Q0-Q7), MveSize enum
- Thumb-2 MVE encoding (VADD/VSUB/VMUL/VDUP/VLDR/VSTR etc.)
- Lane-wise f32x4 div/sqrt via S-register aliasing
Code-generation STPA:
- 4 code-level losses (L-CODE-1..4)
- 9 code-level hazards (H-CODE-1..9) linked to system hazards
- 13 UCAs across 3 controllers (regalloc, instruction selector, encoder)
- 8 loss scenarios with root cause analysis
- 10 system constraints with verification criteria
- 11 code review findings (CR-C1..C5, CR-H2..H8) as rivet artifacts
AGENTS.md generated by rivet init --agents (231 artifacts, 17 types).
851 tests (up from 802), clippy clean, fmt clean.
Implements: FR-002
Implements: FR-005
Fixes: NFR-002
Fixes: NFR-005
Trace: skip
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Critical/High Bug Fixes (from embedded code review)
WASM SIMD → Helium MVE (Cortex-M55)
has_helium()Code-Generation STPA
851 tests (up from 802), AGENTS.md generated (231 artifacts, 17 types)
Test plan
cargo test --workspace— 851 tests, 0 failurescargo clippy— cleancargo fmt --check— clean🤖 Generated with Claude Code