A Rust implementation of a complete AADL (Architecture Analysis and Design Language) toolchain. Parses, validates, analyzes, transforms, and visualizes system architectures per SAE AS5506D. Includes a deployment solver for automated thread-to-processor allocation. Designed for safety-critical systems modeling -- avionics, vehicle software, WASM component architectures, and AI agent workflows.
Spar replaces the Eclipse/Java-based OSATE2 toolchain with a fast, embeddable, WASM-compilable alternative built on rust-analyzer's proven architecture patterns.
# From source
cargo install --git https://github.com/pulseengine/spar
# Or download a pre-built binary from releases
# https://github.com/pulseengine/spar/releases# Parse an AADL model and show the syntax tree
spar parse vehicle.aadl --tree
# List all declared items
spar items vehicle.aadl
# Instantiate a system hierarchy
spar instance --root Pkg::System.Impl vehicle.aadl platform.aadl
# Run all analysis passes
spar analyze --root Pkg::System.Impl vehicle.aadl platform.aadl
# Allocate threads to processors (deployment solver)
spar allocate --root Pkg::System.Impl vehicle.aadl platform.aadl
# Render the architecture as SVG
spar render --root Pkg::System.Impl -o arch.svg vehicle.aadl platform.aadl
# Run verification assertions
spar verify --root Pkg::System.Impl --rules rules.toml vehicle.aadl| Command | Description |
|---|---|
parse |
Parse AADL files and show syntax tree or errors |
items |
List declared packages, types, implementations |
instance |
Build the system instance hierarchy |
analyze |
Run all analysis passes (SARIF/JSON/text output) |
allocate |
Solve thread-to-processor deployment bindings |
diff |
Compare two model versions for structural/diagnostic changes |
modes |
List operational modes and mode transitions |
render |
Generate SVG/HTML architecture diagrams |
verify |
Evaluate verification assertions against the model |
lsp |
Start the Language Server Protocol server |
12 crates, layered from low-level parsing to high-level analysis:
spar-syntax Lossless CST (rowan red-green trees)
spar-parser Recursive descent parser with error recovery
spar-annex AADL annex sublanguage parsing (EMV2, BLESS, BA)
spar-base-db Salsa database for incremental computation
spar-hir-def HIR definitions -- item tree, instance model, arenas
spar-hir Public semantic facade (name resolution, properties)
spar-analysis 27+ pluggable analysis passes
spar-transform Format transforms (AADL <-> WIT, WAC, Rust crates, wRPC)
spar-solver Deployment solver (thread-to-processor allocation)
spar-render SVG architecture diagrams (compound Sugiyama layout)
spar-cli Command-line interface
spar-wasm WebAssembly component (WASI P2)
- 27+ analysis passes -- scheduling, latency, connectivity, resource budgets, ARINC 653, EMV2 fault trees, bus bandwidth, weight/power, mode reachability, and more
- Assertion engine -- declarative verification rules in TOML (
spar verify) - Deployment solver -- automated thread-to-processor allocation with constraint satisfaction
- SARIF output -- analysis results in SARIF format for CI integration
- VS Code extension -- live AADL rendering and diagnostics via LSP
- WASM component -- compiles to a 1.3 MB wasm32-wasip2 component
- Incremental -- salsa-based memoization for fast re-analysis
- Lossless parsing -- every byte preserved in the syntax tree
- Integration plan -- rivet lifecycle integration
- WASM-as-architecture design -- WIT/WAC/wRPC transforms
- VS Code extension design -- editor integration
- Deployment solver plan -- allocation algorithm
Full STPA (System-Theoretic Process Analysis) safety analysis:
- STPA analysis -- losses, hazards, UCAs, loss scenarios
- Safety requirements -- 23 STPA-derived requirements
- Rivet artifacts -- requirements, architecture decisions, verification records
MIT License -- see LICENSE.
Part of PulseEngine -- formally verified WebAssembly toolchain for safety-critical systems