Clarify docs for arm64 packed unwind, RegI=0 RegF>0#5855
Clarify docs for arm64 packed unwind, RegI=0 RegF>0#5855mstorsjo wants to merge 4 commits intoMicrosoftDocs:mainfrom
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The condition CR=0 isn't correct here; the same about the first store for float registers doing the predecrement for any variant where there are no integer registers stored before the floats - this goes for both CR=0, CR=2 and CR=3.
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@mstorsjo : Thanks for your contribution! The author(s) and reviewer(s) have been notified to review your proposed change. |
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CC @pmsjt |
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Learn Build status updates of commit 2008082: ✅ Validation status: passed
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Can you review the proposed changes? IMPORTANT: When the changes are ready for publication, adding a #label:"aq-pr-triaged" |
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The replacement is accurate. When the only case where we get Thank you for the fix @mstorsjo . But we might have to finesse this statement a little better. "the decrement" means which decrement? See, in both the For example: Results in So, we should clarify that this pre-decrement is just to cover for the FP/SIMD registers. This is true even for the results in |
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Clarify the description of the floating-point predecrement behavior
Clarify the predecrement description
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Learn Build status updates of commit 6ee1126: ✅ Validation status: passed
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Learn Build status updates of commit 5dca165: ✅ Validation status: passed
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The condition CR=0 isn't correct here; the same about the first store for float registers doing the predecrement for any variant where there are no integer registers stored before the floats - this goes for both CR=0, CR=2 and CR=3.