diff --git a/config.local/arm64/config.sonic-aspeed b/config.local/arm64/config.sonic-aspeed
index 1323634ef..aa3e11f0d 100644
--- a/config.local/arm64/config.sonic-aspeed
+++ b/config.local/arm64/config.sonic-aspeed
@@ -22,7 +22,8 @@ CONFIG_MDIO_ASPEED=m
 CONFIG_ASPEED_KCS_IPMI_BMC=m
 CONFIG_ASPEED_BT_IPMI_BMC=m
 CONFIG_SPI_ASPEED_SMC=m
-CONFIG_I2C_ASPEED=m
+# CONFIG_I2C_ASPEED is not set
+CONFIG_I2C_AST2600=m
 CONFIG_SPI_ASPEED_TXRX=y
 CONFIG_PINCTRL_ASPEED=y
 CONFIG_PINCTRL_ASPEED_G7=y
@@ -31,6 +32,7 @@ CONFIG_GPIO_ASPEED_SGPIO=y
 CONFIG_GPIO_ASPEED_LTPI=y
 CONFIG_SENSORS_ASPEED=y
 CONFIG_SENSORS_ASPEED_G6=m
+CONFIG_SENSORS_ASPEED_CHASSIS=m
 CONFIG_ASPEED_WATCHDOG=y
 CONFIG_MEDIA_SUPPORT=m
 CONFIG_VIDEO_DEV=m
diff --git a/patches-sonic/nexthop-b27-dts.patch b/patches-sonic/nexthop-b27-dts.patch
new file mode 100644
index 000000000..f0c25b2da
--- /dev/null
+++ b/patches-sonic/nexthop-b27-dts.patch
@@ -0,0 +1,971 @@
+From 9b8f9f3eed5b8732aca6533ddfde184332e254b7 Mon Sep 17 00:00:00 2001
+From: NextHop Build System <build@nexthop.ai>
+Date: Tue, 13 Jan 2026 16:28:15 +0000
+Subject: [PATCH] Add NextHop AST2700 R0 device tree
+
+This adds nexthop-b27-r0.dts for NextHop AST2700 based B27 R0 hardware.
+
+Hardware differences from ast2700-evb:
+- MAC0: Fixed-link (1000Mbps) instead of PHY - direct RGMII to BCM switch
+- MAC1: Disabled (not connected)
+- MDIO0/MDIO1: Disabled (no PHY chips)
+
+The device tree is based on ast2700-evb.dts with modifications for
+production hardware that does not have PHY chips.
+---
+ arch/arm64/boot/dts/aspeed/Makefile          |   1 +
+ arch/arm64/boot/dts/aspeed/nexthop-b27-r0.dts | 930 +++++++++++++++++++
+ 2 files changed, 931 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/aspeed/nexthop-b27-r0.dts
+
+diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspeed/Makefile
+index 4458a1b..486146e 100644
+--- a/arch/arm64/boot/dts/aspeed/Makefile
++++ b/arch/arm64/boot/dts/aspeed/Makefile
+@@ -2,6 +2,7 @@
+ 
+ dtb-$(CONFIG_ARCH_ASPEED) += \
+ 	ast2700-evb.dtb \
++	nexthop-b27-r0.dtb \
+ 	ast2700-raw.dtb \
+ 	ast2700-evb-s0.dtb \
+ 	ast2700-evb-s1.dtb \
+diff --git a/arch/arm64/boot/dts/aspeed/nexthop-b27-r0.dts b/arch/arm64/boot/dts/aspeed/nexthop-b27-r0.dts
+new file mode 100644
+index 0000000..3ca87d4
+--- /dev/null
++++ b/arch/arm64/boot/dts/aspeed/nexthop-b27-r0.dts
+@@ -0,0 +1,930 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++//
++// NextHop AST2700 based B27 R0 Device Tree
++// Based on ast2700-evb.dts with modifications for NextHop B27 card
++
++/dts-v1/;
++
++#include "aspeed-g7.dtsi"
++#include <dt-bindings/gpio/aspeed-gpio.h>
++#include <dt-bindings/net/ti-dp83867.h>
++
++#define PCIE0_EP 0	// 1: EP, 0: RC
++#define PCIE1_EP 0	// 1: EP, 0: RC
++#define PCIE2_RC 0	// 1: RC, 0: SGMII
++
++/ {
++	model = "NextHop B27 R0";
++	compatible = "nexthop,nexthop-b27-r0", "aspeed,ast2700-evb", "aspeed,ast2700";
++
++	chosen {
++		stdout-path = &uart12;
++	};
++
++	firmware {
++		optee: optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
++
++	memory@400000000 {
++		device_type = "memory";
++		reg = <0x4 0x00000000 0x0 0x40000000>;
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		#include "ast2700-reserved-mem.dtsi"
++#if 0
++		video_engine_memory0: video0 {
++			size = <0x0 0x02c00000>;
++			alignment = <0x0 0x00100000>;
++			compatible = "shared-dma-pool";
++			reusable;
++		};
++
++		video_engine_memory1: video1{
++			size = <0x0 0x02c00000>;
++			alignment = <0x0 0x00100000>;
++			compatible = "shared-dma-pool";
++			reusable;
++		};
++#endif
++		gfx_memory: framebuffer {
++			size = <0x0 0x01000000>;
++			alignment = <0x0 0x01000000>;
++			compatible = "shared-dma-pool";
++			reusable;
++		};
++
++		xdma_memory0: xdma0 {
++			size = <0x0 0x01000000>;
++			alignment = <0x0 0x01000000>;
++			compatible = "shared-dma-pool";
++			no-map;
++		};
++
++		xdma_memory1: xdma1 {
++			size = <0x0 0x01000000>;
++			alignment = <0x0 0x01000000>;
++			compatible = "shared-dma-pool";
++			no-map;
++		};
++	};
++#if 0
++	fan0: pwm-fan0 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 0 40000 0>;   /* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan1: pwm-fan1 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 1 40000 0>;   /* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan2: pwm-fan2 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 2 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan3: pwm-fan3 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 3 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan4: pwm-fan4 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 4 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan5: pwm-fan5 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 5 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan6: pwm-fan6 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 6 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan7: pwm-fan7 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 7 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++
++	fan8: pwm-fan8 {
++		compatible = "pwm-fan";
++		pwms = <&pwm_tach 8 40000 0>;	/* Target freq:25 kHz */
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 15 128 255>;
++	};
++#endif
++	iio-hwmon {
++		compatible = "iio-hwmon";
++		status = "okay";
++		io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
++				<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
++				<&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
++				<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
++	};
++};
++
++#if 0
++&pwm_tach {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
++		     &pinctrl_pwm2_default &pinctrl_pwm3_default
++		     &pinctrl_pwm4_default &pinctrl_pwm5_default
++		     &pinctrl_pwm6_default &pinctrl_pwm7_default
++		     &pinctrl_pwm8_default
++		     &pinctrl_tach0_default &pinctrl_tach1_default
++		     &pinctrl_tach2_default &pinctrl_tach3_default
++		     &pinctrl_tach4_default &pinctrl_tach5_default
++		     &pinctrl_tach6_default &pinctrl_tach7_default
++		     &pinctrl_tach8_default &pinctrl_tach9_default
++		     &pinctrl_tach10_default &pinctrl_tach11_default
++		     &pinctrl_tach12_default &pinctrl_tach13_default
++		     &pinctrl_tach14_default &pinctrl_tach15_default>;
++	fan-0 {
++		tach-ch = /bits/ 8 <0x0>;
++	};
++	fan-1 {
++		tach-ch = /bits/ 8 <0x1>;
++	};
++	fan-2 {
++		tach-ch = /bits/ 8 <0x2>;
++	};
++	fan-3 {
++		tach-ch = /bits/ 8 <0x3>;
++	};
++	fan-4 {
++		tach-ch = /bits/ 8 <0x4>;
++	};
++	fan-5 {
++		tach-ch = /bits/ 8 <0x5>;
++	};
++	fan-6 {
++		tach-ch = /bits/ 8 <0x6>;
++	};
++	fan-7 {
++		tach-ch = /bits/ 8 <0x7>;
++	};
++	fan-8 {
++		tach-ch = /bits/ 8 <0x8>;
++	};
++	fan-9 {
++		tach-ch = /bits/ 8 <0x9>;
++	};
++	fan-10 {
++		tach-ch = /bits/ 8 <0xA>;
++	};
++	fan-11 {
++		tach-ch = /bits/ 8 <0xB>;
++	};
++	fan-12 {
++		tach-ch = /bits/ 8 <0xC>;
++	};
++	fan-13 {
++		tach-ch = /bits/ 8 <0xD>;
++	};
++	fan-14 {
++		tach-ch = /bits/ 8 <0xE>;
++	};
++	fan-15 {
++		tach-ch = /bits/ 8 <0xF>;
++	};
++};
++#endif
++&edac {
++	status = "okay";
++};
++
++&mctp0 {
++	status = "okay";
++	memory-region = <&mctp0_reserved>;
++};
++
++&mctp1 {
++	status = "okay";
++	memory-region = <&mctp1_reserved>;
++};
++
++&mctp2 {
++	status = "okay";
++	memory-region = <&mctp2_reserved>;
++};
++
++#if 0
++&sgpiom0 {
++	status = "okay";
++};
++
++&sgpiom1 {
++	status = "okay";
++};
++#endif
++
++&jtag1 {
++	status = "okay";
++};
++
++#if 0
++&adc0 {
++	aspeed,int-vref-microvolt = <2500000>;
++	status = "okay";
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
++		&pinctrl_adc2_default &pinctrl_adc3_default
++		&pinctrl_adc4_default &pinctrl_adc5_default
++		&pinctrl_adc6_default &pinctrl_adc7_default>;
++};
++
++&adc1 {
++	aspeed,int-vref-microvolt = <2500000>;
++	status = "okay";
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
++		&pinctrl_adc10_default &pinctrl_adc11_default
++		&pinctrl_adc12_default &pinctrl_adc13_default
++		&pinctrl_adc14_default &pinctrl_adc15_default>;
++};
++#endif
++
++&pinctrl0 {
++	pinctrl_emmcclk_driving: emmcclk-driving {
++		pins = "AC14";
++		drive-strength = <2>;
++	};
++
++	pinctrl_emmccmd_driving: emmccmd-driving {
++		pins = "AE15";
++		drive-strength = <1>;
++	};
++	pinctrl_emmcdat_driving: emmcdat-driving {
++		pins = "AD14", "AE14", "AF14", "AB13";
++		drive-strength = <1>;
++	};
++};
++
++&pinctrl1 {
++	pinctrl_i3c0_3_hv_voltage: i3chv-voltage {
++		pins = "U25";
++		power-source = <1800>;
++	};
++
++	pinctrl_i3c0_driving: i3c0-driving {
++		pins = "U25", "U26";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c1_driving: i3c1-driving {
++		pins = "Y26", "AA24";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c2_driving: i3c2-driving {
++		pins = "R25", "AA26";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c3_driving: i3c3-driving {
++		pins = "R26", "Y25";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c12_15_hv_voltage: i3chv-voltage {
++		pins = "W25";
++		power-source = <1800>;
++	};
++
++	pinctrl_i3c12_driving: i3c12-driving {
++		pins = "W25", "Y23";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c13_driving: i3c13-driving {
++		pins = "Y24", "W21";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c14_driving: i3c14-driving {
++		pins = "AA23", "AC22";
++		drive-strength = <2>;
++	};
++
++	pinctrl_i3c15_driving: i3c15-driving {
++		pins = "AB22", "Y21";
++		drive-strength = <2>;
++	};
++
++	pinctrl_rgmii0_driving: rgmii0-driving {
++		pins = "C20", "C19", "A8", "R14", "A7", "P14",
++		       "D20", "A6", "B6", "N14", "B7", "B8";
++		drive-strength = <1>;
++	};
++
++	pinctrl_rgmii1_driving: rgmii1-driving {
++		pins = "D19", "C19", "D15", "B12", "B10", "P13",
++		       "C18", "C6", "C7", "D7", "N13", "C8";
++		drive-strength = <1>;
++	};
++};
++
++&gpio1 {
++	pinctrl-0 = <&pinctrl_i3c0_3_hv_voltage &pinctrl_i3c12_15_hv_voltage
++		     &pinctrl_i3c0_driving &pinctrl_i3c1_driving
++		     &pinctrl_i3c2_driving &pinctrl_i3c3_driving
++		     &pinctrl_i3c12_driving &pinctrl_i3c13_driving
++		     &pinctrl_i3c14_driving &pinctrl_i3c15_driving>;
++	pinctrl-names = "default";
++};
++
++#if 0
++&i3c0 {
++	initial-role = "target";
++	pid = <0x000007ec 0x06010000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c1 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c2 {
++	initial-role = "target";
++	pid = <0x000007ec 0x06012000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c3 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c4 {
++	initial-role = "target";
++	pid = <0x000007ec 0x06014000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c5 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c6 {
++	initial-role = "target";
++	pid = <0x000007ec 0x06016000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c7 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c8 {
++	initial-role = "target";
++	pid = <0x000007ec 0x06018000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c9 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c10 {
++	initial-role = "target";
++	pid = <0x000007ec 0x0601A000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c11 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c12 {
++	initial-role = "target";
++	pid = <0x000007ec 0x0601C000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c13 {
++	initial-role = "primary";
++	status = "okay";
++};
++
++&i3c14 {
++	initial-role = "target";
++	pid = <0x000007ec 0x0601E000>;
++	dcr = /bits/ 8 <0xcc>;
++	status = "okay";
++};
++
++&i3c15 {
++	initial-role = "primary";
++	status = "okay";
++};
++#endif
++
++&uart1 {
++	status = "okay";
++};
++&uart12 {
++	status = "okay";
++};
++
++&fmc {
++	status = "okay";
++	pinctrl-0 = <&pinctrl_fwspi_quad_default>;
++	pinctrl-names = "default";
++
++	flash@0 {
++		status = "okay";
++		m25p,fast-read;
++		label = "bmc";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++#include "aspeed-evb-flash-layout-128.dtsi"
++	};
++
++	flash@1 {
++		status = "okay";
++		m25p,fast-read;
++		label = "fmc0:1";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++	};
++
++	flash@2 {
++		status = "disabled";
++		m25p,fast-read;
++		label = "fmc0:2";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++	};
++};
++
++&spi0 {
++	status = "okay";
++	pinctrl-0 = <&pinctrl_spi0_default &pinctrl_spi0_cs1_default>;
++	pinctrl-names = "default";
++
++	flash@0 {
++		status = "okay";
++		m25p,fast-read;
++		label = "spi0:0";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++
++	flash@1 {
++		status = "disabled";
++		m25p,fast-read;
++		label = "spi0:1";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++};
++
++#if 0
++&spi1 {
++	status = "okay";
++	pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1_cs1_default>;
++	pinctrl-names = "default";
++
++	flash@0 {
++		status = "okay";
++		m25p,fast-read;
++		label = "spi1:0";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++
++	flash@1 {
++		status = "disabled";
++		m25p,fast-read;
++		label = "spi1:1";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++};
++#endif
++
++#if 1
++&spi2 {
++	compatible = "aspeed,ast2700-spi-txrx";
++	pinctrl-0 = <&pinctrl_spi2_default>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	spi-aspeed-full-duplex;
++
++	tpm0: tpmdev@0 {
++		compatible = "tcg,tpm_tis-spi";
++		spi-max-frequency = <25000000>;
++		reg = <0>;
++		status = "okay";
++	};
++};
++#else
++&spi2 {
++	compatible = "aspeed,ast2700-spi";
++	pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2_cs1_default>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	flash@0 {
++		status = "okay";
++		reg = < 0 >;
++		compatible = "jedec,spi-nor";
++		m25p,fast-read;
++		label = "spi2:0";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++
++	flash@1 {
++		status = "okay";
++		reg = < 1 >;
++		compatible = "jedec,spi-nor";
++		m25p,fast-read;
++		label = "spi2:1";
++		spi-max-frequency = <50000000>;
++		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <2>;
++	};
++};
++#endif
++
++#if 0
++&can0 {
++	status = "okay";
++};
++#endif
++
++&emmc_controller {
++	status = "okay";
++	mmc-hs200-1_8v;
++};
++
++&emmc {
++	status = "okay";
++#if 1
++	bus-width = <4>;
++#else
++	bus-width = <8>;
++	pinctrl-0 = <&pinctrl_emmc_default
++		     &pinctrl_emmcg8_default>;
++#endif
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_emmc_default &pinctrl_emmcclk_driving &pinctrl_emmccmd_driving &pinctrl_emmcdat_driving>;
++
++	non-removable;
++	max-frequency = <200000000>;
++};
++
++#if 0
++&ufs_controller {
++	status = "okay";
++};
++
++&ufs {
++	status = "okay";
++	lanes-per-direction = <2>;
++	ref-clk-freq = <26000000>;
++};
++#endif
++
++&chassis {
++	status = "okay";
++};
++
++&mac0 {
++        status = "okay";
++        /*compatible = "brcm,bcm53134";*/
++        phy-mode = "rgmii-id";
++        pinctrl-names = "default";
++        pinctrl-0 = <&pinctrl_rgmii0_default &pinctrl_rgmii0_driving>;
++        fixed-link {
++                speed = <1000>;
++                full-duplex;
++                pause;
++        };
++};
++
++&mdio0 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	switch@1e {
++		compatible = "brcm,bcm53134";
++		reg = <0x1e>;
++
++		dsa,member = <0 0>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* Port 0 - External RJ45 with internal PHY */
++			port@0 {
++				reg = <0>;
++				label = "rj45";
++				phy-handle = <&switch0phy0>;
++			};
++
++			/* Port 5 - x86 with internal PHY */
++			port@5 {
++				reg = <5>;
++				label = "x86";
++				phy-handle = <&switch0phy5>;
++			};
++
++			/* Port 8 - IMP to AST2700 MAC0 */
++			port@8 {
++				reg = <8>;
++				label = "cpu";
++				ethernet = <&mac0>;
++				phy-mode = "rgmii-id";
++				fixed-link {
++					speed = <1000>;
++					full-duplex;
++					pause;
++				};
++			};
++		};
++
++		/* BCM53134 internal MDIO bus for internal PHYs */
++		mdio {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			switch0phy0: ethernet-phy@0 {
++				reg = <0>;
++			};
++
++			switch0phy5: ethernet-phy@5 {
++				reg = <5>;
++			};
++		};
++	};
++};
++
++
++&syscon1 {
++	assigned-clocks = <&syscon1 SCU1_CLK_MACHCLK>,
++			  <&syscon1 SCU1_CLK_RGMII>,
++			  <&syscon1 SCU1_CLK_RMII>;
++	assigned-clock-rates = <200000000>, <125000000>, <50000000>;
++};
++
++&espi0 {
++	status = "okay";
++	perif-dma-mode;
++	perif-mmbi-enable;
++	perif-mmbi-src-addr = <0x0 0xa8000000>;
++	perif-mmbi-tgt-memory = <&espi0_mmbi_memory>;
++	perif-mmbi-instance-num = <0x1>;
++	perif-mcyc-enable;
++	perif-mcyc-src-addr = <0x0 0x98000000>;
++	perif-mcyc-size = <0x0 0x10000>;
++	perif-rtc-enable;
++	oob-dma-mode;
++	flash-dma-mode;
++#if 0	// if support eDAF MIX mode, open this if case to use sample code
++	flash-edaf-mode = <0x0>;
++	flash-edaf-tgt-addr = <&edaf0>;
++	flash-edaf-size = <0x0 0x4000000>;
++#endif
++};
++
++&rtc_over_espi0 {
++	status = "okay";
++};
++
++#if 0
++&lpc0_kcs0 {
++	status = "okay";
++	kcs-io-addr = <0xca0>;
++	kcs-channel = <0>;
++};
++
++&lpc0_kcs1 {
++	status = "okay";
++	kcs-io-addr = <0xca8>;
++	kcs-channel = <1>;
++};
++
++&lpc0_kcs2 {
++	status = "okay";
++	kcs-io-addr = <0xca2>;
++	kcs-channel = <2>;
++};
++
++&lpc0_kcs3 {
++	status = "okay";
++	kcs-io-addr = <0xca4>;
++	kcs-channel = <3>;
++};
++#endif
++
++&rtc {
++	status = "okay";
++};
++
++
++&jtag0 {
++	status = "okay";
++};
++
++&sdio_controller {
++	status = "disabled";
++	mmc-hs200-1_8v;
++
++	vcc_sdhci0: regulator-vcc-sdhci0 {
++		compatible = "regulator-fixed";
++		regulator-name = "SDHCI0 Vcc";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpios = <&gpio1 ASPEED_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
++	vccq_sdhci0: regulator-vccq-sdhci0 {
++		compatible = "regulator-gpio";
++		regulator-name = "SDHCI0 VccQ";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <3300000>;
++		gpios = <&gpio1 ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
++		gpios-states = <1>;
++		states = <3300000 1>,
++			 <1800000 0>;
++	};
++
++};
++
++&sdhci {
++	status = "disabled";
++	bus-width = <4>;
++	max-frequency = <100000000>;
++	/* DDR50 bits in CAPA2 are not supported */
++	sdhci-caps-mask = <0x6 0x0>;
++	sdhci-drive-type = /bits/ 8 <3>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_sd_default>;
++	vmmc-supply = <&vcc_sdhci0>;
++	vqmmc-supply = <&vccq_sdhci0>;
++	sd-uhs-sdr104; /* enable sdr104 to execute tuning */
++};
++
++#if 1
++&i2c0 {
++	status = "okay";
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++};
++
++&i2c5 {
++	status = "disabled";
++};
++
++&i2c6 {
++	status = "okay";
++};
++
++&i2c7 {
++	status = "okay";
++};
++
++&i2c8 {
++	status = "okay";
++};
++
++&i2c9 {
++        status = "okay";
++};
++
++&i2c10 {
++        status = "okay";
++};
++
++&i2c11 {
++	status = "okay";
++};
++
++&i2c12 {
++	status = "okay";
++};
++
++&i2c13 {
++	status = "disabled";
++};
++#endif
++
++#if 0
++&ehci0 {
++	status = "okay";
++};
++#endif
++
++&vhubb0 {
++	status = "disabled";
++};
++
++&vhubb1 {
++	status = "okay";
++	pinctrl-0 = <&pinctrl_usb2bd1_default>;
++};
++
++#if 0
++&vhuba0 {
++        status = "okay";
++        pinctrl-0 = <&pinctrl_usb2ahpd0_default>;
++};
++#endif
++&wdt0 {
++	status = "okay";
++};
++
++&wdt1 {
++	status = "okay";
++};
++
++&otp {
++	status = "okay";
++};
++
+-- 
+2.34.1
+
diff --git a/patches-sonic/series b/patches-sonic/series
index 54a1e5208..f086e61a6 100644
--- a/patches-sonic/series
+++ b/patches-sonic/series
@@ -222,6 +222,7 @@ cisco-npu-disable-other-bars.patch
 
 ###-> aspeed
 aspeed-ast2700-support.patch
+nexthop-b27-dts.patch
 ###-> aspeed-end
 
 #