From 023d1b238b424d8c2f65d6916884290b89bd0747 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 16 Mar 2026 14:53:21 +0800 Subject: [PATCH] FROMLIST: phy: qcom: qmp-pcie: Add nocsr reset list and number for Kaanapali The nocsr reset handling was refactored to support multiple nocsr resets required for PHY configurations with bifurcated operation modes. Add required nocsr_reset_list and num_nocsr_resets for Kaanapali. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-3-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 474a11b15c2a..29bc0fe5ce37 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4669,6 +4669,8 @@ static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .nocsr_reset_list = sm8550_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout,