[SPIR-V] 16-bit stores emit 32-bit stores with masking

[takayhan-AMD]

Description
DXC generates 32-bit store op with masking for a 16-bit store into a RWByteAddressBuffer. This is functionally correct for a single thread, but broken fundamentally when multiple lanes access adjacent memory to modify, i.e. lane0's higher WORD would be lane1's lower WORD.

Steps to Reproduce
HLSL example: https://godbolt.org/z/W1sxM63ro
Command line: dxc -T cs_6_6 -E main -enable-16bit-types -spirv -HV 2021 -fvk-use-scalar-layout -fcgl

Actual Behavior
The GLSL example below shows in SPIR-V how 16-bit store would instead be generated correctly.
https://godbolt.org/z/vjMqj83Gf

Environment

• DXC version: Trunk
• Host Operating System: Windows 11